In the control and regulation of motor vehicles, various regulation and control tasks are usually divided among several processors. When several processors are present, in many cases at least two processors jointly access the same memory.
Difficulties occur if different processors access the same memory cell at the same time. In order to prevent this, complicated measures are taken to ensure that more than one processor do not access the same memory cell at the same time.
Objects of the present invention include, but are not limited to, ensuring the reliability of data transmission between processors, minimizing delays due to data exchange between processors, and optimizing the operating time burden on individual processors as well as the overall system when different processors access the same memory.